Date of Completion

8-24-2011

Embargo Period

9-8-2011

Advisors

Dr. John Chandy; Dr. Lei Wang

Field of Study

Electrical Engineering

Degree

Master of Science

Open Access

Campus Access

Abstract

As we enter into sub-nanometer technologies in order to increase performance of CMOS devices, reliability issues such as negative bias temperature instability (NBTI), hot carrier injection (HCI), time dependent dielectric breakdown (TDDB), and electromigration (EM) are coming up as potential threats to superior performance in the field. All these reliability issues cause intermittent failures and finally cause the performance of the chips to degrade over time. In this thesis, the primary focus is on NBTI and HCI for which both cause temporal degradation in performance of nanoscale integrated circuits. This research studies and analyzes the temporal delay degradation of logic circuits due to NBTI and HCI effects on a 90nm test chips. From the experiments conducted, frequency degradation due to NBTI is about 2.5% - 3% after the chip is stressed using burn-in at an elevated voltage of 1.8 volts and 135°C temperature. AC stress test was also performed by providing AC signals of different duty ratio to the test chip in order to study the impact of aging effects on different ring oscillator chains. Key contribution of this thesis includes extracting the real silicon data from the 90nm test chips by designing a test board, separating HCI and NBTI effects by developing novel mathematical model and performing detailed aging analysis.

Major Advisor

Dr. Mohammad Tehranipoor

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