A hierarchical memory I/O interface architecture for high-speed data communications
Date of Completion
January 1998
Keywords
Engineering, System Science|Computer Science
Degree
Ph.D.
Abstract
The conventional workstation may not be sufficient enough for the bandwidth provided by the high-speed networks due to the performance bottleneck in the I/O subsystem. Specifically, the “delayed acknowledgment” and “windowing out” problems may severely damage system performance. In this work, we propose a novel I/O subsystem architectural design with the hierarchical I/O memories (HIOM) to address these problems and to support the highly pipelined data transmissions in high-speed network environment. The HIOM architecture effectively reduces the data blocking by moving data between the different levels of the I/O buffers. It also provides large receiving I/O buffer space to offset the effect of network propagation delay during the long-distance communications. ^
Recommended Citation
Gan, Qi, "A hierarchical memory I/O interface architecture for high-speed data communications" (1998). Doctoral Dissertations. AAI9918069.
https://digitalcommons.lib.uconn.edu/dissertations/AAI9918069