High-Quality Test and Diagnosis for Small-Delay Defects
Date of Completion
January 2010
Keywords
Engineering, Electronics and Electrical
Degree
Ph.D.
Abstract
The scaling of fabrication technology not only provides us higher integration and enhanced performance in the design, but also the increased manufacturing defects. As a result, the stuck-at fault test alone cannot guarantee high test quality and in-field reliability. At-speed delay test using transition delay fault (TDF) model has been widely used in industry to detect the timing-related defects. The small-delay defect (SDD) is one type of such timing defects, which can be introduced by imperfect manufacturing process as well as pattern-induced on-chip noises, e.g., power supply noise (PSN) and crosstalk, causing chip failures by introducing extra delay to the design. As technology scales to 45nm and below, testing for SDDs is necessary to ensure the quality and reliability of high-performance integrated circuits. ^ The traditional at-speed test methods cannot ensure high test coverage of SDDs with a reasonable pattern count. As a result of semiconductor industry demand, commercial timing-aware automatic test pattern generation (ATPG) tools have been developed for SDD detection. However, these ATPG tools suffer from large pattern count and CPU runtime. Furthermore, none of these methodologies take into account the impact of design parameter variations and on-chip noises, e.g., process variations, PSN and crosstalk, which are potential sources of SDDs. Furthermore, it is vital to diagnose the SDD failures and show which are the major causes of the chip failures.^ In this research, we propose new techniques and methodologies to improve the overall test quality of SDDs with a very small pattern set. From the implementation of the proposed procedures on both academic and industry circuits, our methods can result in a pattern count as low as a traditional 1-detect pattern set and long path sensitization and SDD detection similar or even better than the n-detect or timing-aware pattern set. The important design parameters and pattern-induced noises such as process variations, PSN and crosstalk are taken into account in the proposed methodologies. The new diagnosis flow is also proposed to identify whether the failure is caused by PSN, or crosstalk, or a combination of them. ^
Recommended Citation
Peng, Ke, "High-Quality Test and Diagnosis for Small-Delay Defects" (2010). Doctoral Dissertations. AAI3464355.
https://digitalcommons.lib.uconn.edu/dissertations/AAI3464355