Date of Completion

8-24-2015

Embargo Period

8-23-2016

Keywords

Transistors, TCAD, Threshold Voltage, Electrical Engineering, Microfabrication

Major Advisor

Ali Gokirmak

Co-Major Advisor

Helena Silva

Associate Advisor

Arvind Kumar

Associate Advisor

See above

Field of Study

Electrical Engineering

Degree

Doctor of Philosophy

Open Access

Open Access

Abstract

Current leakage on a planar field effect transistor (FET) channel’s side surfaces is more significant as the channel width decreases. Traps and positive fixed charges at the interface of Silicon and the isolation dielectric (STI) are mainly responsible for this. An accumulated body approach introduces a side-gate structure surrounding the body of the transistor, which can be used to accumulate the body in narrow structures to suppress the leakage. A separately controlled top gate is used for transistor action.

In this work, the fabrication process and electrical behavior of short and narrow-channel (10 nm scale) bulk Si accumulated body MOSFETs are analyzed through three-dimensional numerical studies. Results are verified experimentally with devices fabricated at IBM Watson Research Labs using conventional CMOS processes.

Simulation results show suppression of leakage currents by 106 times for no side-interface charges and by 1010 times for an interface positive fixed charge density of 1012 cm-2. The threshold voltage (VT) can be dynamically controlled by the side-gate through accumulation of the body. For simulated structures of W x L = 10 nm x 15 nm, VT shift per a negative volt of side-gate bias (ΔVT/ΔVside) is more than 0.3 V/V. For experimental devices of effective W x L = 15 x 27 nm, ΔVT/ΔVside ratio is more than 1 V/V. Reliable high temperature (> 600 K) operation and improvement in subthreshold slope and drain induced barrier lowering is also shown in simulations and in experimental structures.

Various steady-state and AC analyses are also conducted to characterize the effect of the side-gate and its relation to other terminals. One such relationship exists between the side-gate and the substrate, where the capacitive coupling of the side-gate enhances the depletion effect of substrate biasing. It is shown through simulations, and verified through experiments, that although the mechanisms of VT control by the side-gate and substrate biasing are different, they enhance the effect of each other.

Furthermore, the effect of line edge roughness on active area of the MOSFET is analyzed through numerical analysis and it is shown that the side-gate of an accumulated body MOSFET helps direct the current towards the center of the channel.

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