Date of Completion
4-8-2013
Embargo Period
4-8-2013
Keywords
Design-for-test, low-power test, power bumps, flip-chip, test power analysis
Major Advisor
Mohammad Tehranipoor
Associate Advisor
John Chandy
Associate Advisor
Lei Wang
Associate Advisor
Omer Khan
Field of Study
Electrical Engineering
Degree
Doctor of Philosophy
Open Access
Open Access
Abstract
Power consumption has not only become a critical concern in VLSI design phase, but also in test phase. This work focuses on power during test, covering two major research topics: test power analysis and test power reduction. For the analysis part, we firstly demonstrate our basic switching and weighted switching activity analysis in various test phases, pattern set, benchmarks. Then, we propose a layout-aware power analysis flow, with the capability of performing IR-drop analysis, peak current analysis. This flow is integrated in test pattern simulation and is able to monitor power and current behavior across the entire test session, without introducing much CPU run time overhead. It is an universal power analysis methodology that can be applied to various digital designs, technologies, as well as handling low power design features. For the test power reduction part, we proposes a power sensitive scan identification flow to help identify and gate scan cells so as to reduce shift power without introducing much power overhead in capture mode.
Recommended Citation
Zhao, Wei, "Vector-based Peak Current Analysis during Wafer Test of Flip-chip Designs" (2013). Doctoral Dissertations. 37.
https://digitalcommons.lib.uconn.edu/dissertations/37