Date of Completion

11-30-2019

Embargo Period

11-29-2019

Keywords

embedded system design, hardware security, physical layer, security countermeasure, VLSI

Major Advisor

Lei Wang

Associate Advisor

John Chandy

Associate Advisor

Zhijie Shi

Field of Study

Electrical Engineering

Open Access

Open Access

Abstract

Security in embedded system design, which has long been a critical problem for ensuring the confidentiality, data integrity and system reliability for embedded system designers and users, is now facing a new dimension of threat from the attacks on hardware. As the IC design reaches sub-micron regime, increased sensitivity of device under environmental condition has made some new types of attacks possible, while the analysis and detection for design vulnerabilities against these attacks are harder on the much more complicated designs nowadays. In the meanwhile, more efficient and diverse attack methodologies are developed by attackers as the technology advances. On the other hand, embedded system has limitations on the hardware resources and power consumption which can be allocated for preventive or defensive countermeasures. The future trends of system development, including cloud computing, distributed network and internet-of-things (IoT) are also pushing the edge of such limitations on embedded system designs. Low cost, high efficiency, and flexible hardware security design methodologies are needed for the current IC production ow as well as the future application scenarios. In this thesis, we're presenting several efforts made towards low cost and high efficiency embedded hardware security design and analysis. First, the finite state machine based circuit vulnerability analysis framework is proposed. Second, we demonstrated a secure scan architecture design which utilizes novel property of memristor devices. Lastly, a side channel resilience design methodology is presented for FPGA bitstream protection.

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