Date of Completion

5-2-2017

Embargo Period

5-2-2017

Keywords

Reconfigurable Logic; Nonvolatile Logic; flip-flops; PCM NANOR; PCM-NAND; PCM-NOR; PCM adder; PCM XOR; PCM State Machines

Major Advisor

Ali Gokirmak

Associate Advisor

Helena Silva

Associate Advisor

Omer Khan

Field of Study

Electrical Engineering

Degree

Doctor of Philosophy

Open Access

Open Access

Abstract

Memory access latencies are some of the major limitations on data intensive computation performance nowadays. The possibly achievable CPU clock frequencies must be limited to the maximum access speed of the off-chip memory which constrains the overall system speed, regardless of the power consumption constraints. This computational bottleneck is commonly referred to as the Von-Neumann bottleneck. Memory access latencies can be drastically decreased by integrating the main memory onto the CPU. Phase change memory (PCM) provides the possibility of integration of high-density high-speed non-volatile memory banks on top of the CMOS layer. This computer-on-chip concept has the potential to achieve up to 3-4 orders of magnitude of improvement in computation speed depending on the application. The performance of this computer-on-chip system can be further improved by having the ability to perform logic operations in the memory layer which will also relieve and better utilize the underneath CMOS real estate.

The operation principles and the materials properties of PCM devices allow implementation of functional multi-contact phase-change devices that can be integrated alongside the memory arrays. In this dissertation, a family of multi-contact phase-change devices that are capable of achieving various nonvolatile logic functionalities are proposed. The operation of the proposed devices is demonstrated through unified electro-thermal and materials models that self-consistently solve the current continuity, heat transfer and phase field equations in COMSOL Multiphysics. The access transistors are modeled using COMSOL nFET SPICE model. The functionality of these devices relies on the novel utilization of the thermal runaway and thermal crosstalk phenomena that PCM devices experience and are often referred to as challenges that need to be overcome. The proposed devices are able to achieve: multiplexing and signal routing, simultaneous NAND & NOR, simultaneous AND & XOR (hence a single device half adder) and JK and T flipflops operation as well as multi-bit state machines. When compared to their conventional CMOS counterparts the proposed devices can offer up to 66% area reduction with the added feature of nonvolatility. The results show the promising potential of the proposed devices for complementing high-performance VLSI as well as reconfigurable-logic.

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