Date of Completion


Embargo Period



Reliability, aging, performance, design, test, process variations, testing, patterns, timing analysis

Major Advisor

Dr. Mohammad Tehranipoor

Associate Advisor

Dr. John Chandy

Associate Advisor

Dr. Lei Wang

Field of Study

Electrical Engineering


Doctor of Philosophy

Open Access

Open Access


The rapid scaling of CMOS technology into the 45nm feature node or below enables the design of higher performance chips through the construction of complex and powerful circuitry. Under area and power constraints similar to those of the past, circuit performance can raise to multi-GHz. The major impulse is that current design can provide an abundance of functionalities with a compacted layout of millions of transistors in a small chip area. However, shrinking transistor dimensions and highly condensed design layout inevitably raise reliability issues including a notable impact on performance, e-specially aging effects and process variations. The timing uncertainties introduced by these factors cause path delays to deviate considerably from their deterministic values and to span to a wide range. Consequently, transistor and gate capabilities are degraded. Circuits experience aggravated performance degradation, increased yield loss and escape, and a reduced operational lifetime. Circuit reliability analysis at the pre-silicon stage has become vital for sub-45nm technology designs to detect aging effects in particular, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). Meanwhile, clock tree, the most active component in a circuit, experiences a severe skew problem. Traditional load-matching and zero-skew routing techniques are not as effective upon aging effects and process variations as they are in large node technologies. In addition, structure tests are required to ensure that the products delivered to customers satisfy design specifications. Of all test methods, the path delay fault (PDF) test is the most effective method to bin the circuit frequency and evaluate the circuit performance. Considering aging effects and process variations, conventional PDF pattern generation and tests face the problems of test complexity and high test cost. This thesis targets these challenging issues in reliable integrated circuits designs and tests to deal with the performance impacts. The techniques developed here include: (1) A comprehensive analysis of the importance of performance impacts, including two major aging effects, NBTI and HCI. (2) A novel methodology, named aging-aware path delay (APD) analysis flow. APD flow is developed based on current commercial tools to guarantee its high accuracy and low CPU runtime on circuit-level aging analysis. (3) A selective gate sizing method, which makes use of APD flow analysis results. This method is proposed to efficiently mitigate reliability threats and requires minimal area overhead. (4) A representative critical reliability path design to construct stand-alone circuitry for accurate performance evaluation and path delay deviation measurement. (5) A novel flow for reducing clock skew with high efficiency. This flow takes into ac- count the impact of NBTI and process variations. (6) A novel test cost reduction flow. Post-silicon measurements on the ring-oscillators (ROs) facilitate the prediction of actual delay variations. Path delays are ranked accordingly, and PDF patterns are thus reduced. (7) A novel methodology for identifying testable representative paths (TRPs) for path delay fault tests. This technique reduces PDF patterns and saves test cost and time considering both NBTI effect and process variations. These methodologies are proposed to address challenging issues to design reliable integrated circuits, and to provide a pathway for the successful design and testing of unpredictable silicon at sub-45nm technologies.