Energy-efficient Signal Processing for CMOS and Beyond: From Algorithm to Architecture

Date of Completion

January 2011


Engineering, Electronics and Electrical




Achieving energy efficiency for signal processing hardware platform is a goal that has been pursued in various layers of electronic system, from system, algorithm, architecture, circuit to device. In this work, we target embedded DSP systems, identify four emerging research areas from system to architecture level, and develop a suite of techniques to improve energy efficiency in signal processing. At the system level, we investigate the distributed embedded system powered by renewable energy, propose a novel RF power management algorithm to increase the power efficiency. Considering time-varying fading channels and statistical energy harvesting processes, we propose to turn on RF circuits only when the channel gain is higher than a threshold, and adjust the RF power according to the energy availability to improve the overall data rate. Exploiting the fact that the optimal threshold is a function of variable renewable energy subject to environmental changes, we adaptively adjust the threshold in accordance with renewable energy to improve energy efficiency. At algorithm level, we develop two schemes to reduce the energy for wireless transmission. First, we propose a cooperative diversity algorithm to reduce the transmission power in fading channels. Cooperative nodes shift the carrier frequency of the source node, and the destination node receives the signal from the source node and the cooperative nodes as a standard orthogonal frequency division multiplexing (OFDM) receiver. Power consumption optimization is achieved via cooperative scale design to balance diversity gain and cooperative overhead. Then we study nonbinary low-density parity-check (LDPC) codes. A decoder architecture based on a novel decoding algorithm referred to as Adaptive Message Control (AMC) for nonbinary low-density parity-check (LDPC) codes is proposed. AMC can significantly reduce the operation complexity of the decoder by adaptively truncating the trivial entries in messages. Finally, we propose to improve the energy efficiency of key signal processing unit using nano-electronic. A new nanosystem architecture that employs nanowire crossbars for digital signal processing (DSP) applications is developed. Distributed arithmetic is utilized such that complex signal processing computation can he mapped into regular memory operations. A novel defect/error-tolerant technique that exploits algorithmic error compensation is proposed. ^