On-chip Structures for Reliable and Secure Integrated Circuits Design

Date of Completion

January 2010


Engineering, Electronics and Electrical




As technology scales to 65nm and below, aging, noise and variations in integrated circuits (IC) and systems have become the major challenges to semiconductor and EDA industry. As a result, the deviation between predicted IC performance using simulation tools and actual IC performance on silicon increases significantly. Furthermore, in Giga Hertze era, off-chip equipments have the problems of high cost and accuracy loss due to parasitics. Therefore, accurate and low-cost on-chip sensors are in great need. This dissertation focuses on the design of low-cost, accurate, and robust on-chip sensors, to capture various effects during circuit operation. The sensors are able to perform various measurements including, delay, IR-drop, aging, and process variations. The design of these sensors have been completed and the path-delay, IR-drop and negative bias temperature instability (NBTI) sensors have been inserted into a 55nm industrial SOC test chip. In addition, a novel low-cost delay configurable line (DCL) based sensor has been designed to perform parametric test for analog devices. The last part of this dissertation is the development of a novel sensor called physical unclonable function (PUF), which is employed to generate unique signature for IC identification and authentication purpose. Different from existing PUFs, which exploit only process variations for generating IC signature, the new PUF, called PE-PUF, takes into account both process and environmental variations for IC signature generation. This improvement magnifies chip-to-chip signature randomness and uniqueness.^