High quality delay tests for very deep submicron designs

Date of Completion

January 2007


Engineering, Electronics and Electrical




To meet the market demand, next generation of technology appears with increasing speed and performance driving manufacturing process to its limit. The, demand for low power consumption in battery operated devices, higher frequency and higher functional density has introduced new challenges to design and test engineers. Reducing power supply will lower the total power consumption but increases the circuit sensitivity to noise since the transistor threshold voltage is not scaling proportionally. Higher frequency and functional density will increase the power consumption producing more heat in the design and result in larger power supply noise. Integration of several cores for higher performance and throughput leads to longer interconnects thereby increasing coupling capacitance. As a result, performance verification has become one of the most challenging tasks for nanometer technology designs. ^ Delay test has gained popularity in industry over the past several years as a reliable method for post-silicon performance verification. Industry began using functional patterns first, but as the design size became larger, high cost of generation as such patterns usually are generated manually, and low fault coverage forced functional at speed test as a supplement to structural test in many semiconductor companies' design-for-test (DFT) flow. Instead, scan-based delay fault test methods gained attention primarily due to the very high fault coverage and their simple procedure to generate patterns. Scan-based path delay fault test and transition delay fault test, together, can provide a high quality test. However, there are new challenges surfacing in nanometer technologies mainly due to the difference in the operating conditions during test mode and normal mode. For instance, power during test mode is 2-3X higher than normal mode resulting in higher power supply noise which in turn impacts circuit performance. Other important issues include implementation of scan-based methods using low-cost testers, improving fault coverage and reducing pattern count. Increasing population of small delay defects also need to be considered as they present quality and reliability issues. This thesis address these issues and present novel DFT architectures and pattern generation solutions to the above problems. ^